interface interface_uart (input PCLK , input PRESETn);

    //Signals Declaration 
    logic txd;
    logic rxd;

    //clocking blocks
    clocking driver_cb @(posedge PCLK);
        default input #1 output #1;
        output txd;
    endclocking
  
    clocking monitor_cb @(posedge PCLK);
        default input #1 output #1;
        input   rxd;  
    endclocking
  
    //modports
    modport DRIVER  (clocking driver_cb , input PCLK,PRESETn);
    modport MONITOR (clocking monitor_cb , input PCLK,PRESETn);

endinterface
